Demand for ever decreasing chip fabrication costs forces the industry to develop new solutions for inexpensive and reliable chip testing devices. A central component for repetitively contacting contact arrays of tested circuit chips is an interconnect assembly that is placed adjacent a test apparatus contact array that has contact pitch corresponding to the tested chips' carrier (package) contact pitch. During packaged chip testing, a package is brought with its contact array into contact with the interconnect assembly such that an independent conductive contact is established between each of the package's contacts and the corresponding contact of the test apparatus.
A first important aspect for reliable performance of a test apparatus is the interconnect assembly's ability to establish conductive contact with constant minimum electrical resistance to the tested chip over a maximum number of test cycles. For that purpose, multiple conductive paths are desirable between each pair of opposing contacts to level contact resistance fluctuations and to reduce the total transmission resistance of the interconnect stage.
In addition, eventual oxide and contaminant layers need to be removed by a scratching movement of the interconnect assembly's contact tips along the test contact surfaces. In addition, each of the assembly's interconnect stages needs to provide a maximum contacting flexibility to resiliently compensate for dimensional discrepancies of the tested contacts. The present invention addresses these needs.
A second aspect for reliable performance is minimum fatigue of the involved parts such that a constant contacting force is maintained for a maximum number of test cycles. Prone to fatigue in common interconnect assemblies are peak stress regions of repetitively elastically deformed interconnect members. Also commonly affected by fatigue failure is the connecting interface of the conductive structure with the non conductive carrier structure, which tends to delaminate as a result of repetitive high peak load changes in the interface. The present invention addresses these issues.
For a cost effective and reliable fabrication of interconnect assemblies there exists a need for a interconnect configuration that requires a minimum number of involved fabrication steps and individual components. Fabrication steps are preferably performed along a single axis. Assembling operations are preferably avoided. The present invention addresses this need.